Digital IC Trainer (VPL-DL-DICT)

To fulfil the variegated demands and requirements of numerous patrons, we are instrumental in offering Digital IC Trainer. It is prepared by making use of the top quality components and latest techniques. Apart from this, it is available at the nominal rates.

Features:

• Power efficiency
• High work capacity
• Durable

Technical Specifications:

• DC Supplies: 5V/500mA
• Clock Generators:
• Fixed: 0.1Hz, 1Hz (simultaneous 5Vindependent outputs)
• Variable: One low-frequency variable clock generator
• Manual Pulser: One independent buffered bounceless manual pulser (useful to freezing the action of each stage of the counter after every clock pulse).
• Logic Level Inputs: Eight independent buffered logic level inputs to select high/low TTL levels, each with a LED to indicate high/low staturs and termination.
• Logic Level Indicators: Eight independent buffered logic level indicators for High/low status indication of digital outputs.
• Power ON: Power ON switch with indicator for mains on indication and fuse for protection.
• Patch Cords: Set of 20 assorted coloured multi-stand wires with 2mm stackable plug termination at both ends.
• Power Requirement: 230 ±10%V AC, 50Hz, single phase.
• Accessories: Instruction Manual.

Experiments:

• Study of basic gates and verification of their truth tables (NOT, OR, AND, NOR, NAND, EX-OR, EX-NOR).
• Study and verifications of the laws of Boolean Algebra and Demorgan’s theorem.
• Study of important TTL terminologies, verification of important TTL circuit parameters.
• Construction and verifications of various types of flip-flops using gates & IC’s (RS, JK, D, T, M/SJK).
• Construction and verification of various types of combinational circuits such as Half Adder, Full Adder, Half Subtractor, Full Subtractor, Even/Odd Parity Checker, Multiplexer, Demultiplexer, Binary to Gray & Gray to Binary converters.
• Construction and verification of various types of Up/Down, Synchronous Asynchronous, Ripple, Reverse, Ring, Binary, BCD & Decade Counters.
• Construction and verifications of 4 bit universal shift register (SR/SL operation).
• Study of 7-segment display and decoder/driver.