Parallel Port Based 48 Channel Logic Analyzer (VPL-PPLA-48)
No. of Channels : 48
Frequency : 50 MHz.
Input Impedance : 1 M Ohm. input capacitor: <5P
Input Voltage : +25V transient +10V continuous
Threshold Voltage : TTL (1.4V).
Setup Time : 4 μsec in internal mode 0 μsec in external mode
Hold Time : 0 μsec in internal mode 8 μsec in external mode
Trigger Format : “0”, “1”. “Xs”.
Trigger Setup Time : More than 20 μsec.
Trigger Position : 128 to 1920 data before trigger and 1920 to 128 data after trigger in 100 MHz mode. 64 to 960 data before trigger and 960 to 64 data after trigger in other frequency.
Memory Capacity : 1k data/every channel.
Display State : ASCII, Binary, Decimal, Hexadecimal in one screen at one time.
Display Timing : 24 Channel waveform in one screen. The display indicates the time between the cursor 1 and cursor 2.
Repeat : Automatically starts a new data acquisition one second after the completion of the previous one.
Repeater on Trigger : Automatically starts a new data acquisition cycle after the completion of last cycle and upon detection of trigger word.
Files : Save and Load data, Delete and Rename catalog files.
Printer : Print all data on screen to printer
Note: Specifications can be changed, added or subtracted without notice in our constant efforts for improvement.