34 Channel Timing-state Logic Analyzer (VPL-LA1034)


  • Sampling frequency: 125MHz<max)
  • Realtime display sampling frequency: 125Mhz(Max)
  • Synchronous sampling rate: 125M(external CLK cable)
  • CH memory depth: 512Kbits
  • Input resistance: 100KΩ
  • Input signal range: 0~5V
  • USB version: USB2.0 high speed
  • Power supply: USB
  • Trigger: level trigger, edge trigger, external trigger
  • Data dynamic record: support
  • System: Windows 2000, Windows XP, Windows 7(32&64)

vpl-la-1034 b


  • sampling cycle could set as 8ns, 10ns, 20ns, 50ns, 100ns, 200ns, 500ns,1us…100ms, it also means from 125MHZ, 100MHZ to 10HZ
  • Support 125M external synchronous time
  • Adopts high compression algorithm, compression rate will auto adjust from 1:1 to 1^37:1. If 125M sampling, 1024S has 36Bit memory
  • Adopts CYPRESS synchron memory chip, capacity is 512K*36BIT, Width 125M*36BIT.
  • With external trigger signal cable TRG, support high/low level trigger.
  • Support SPI UART PWM I2C protocol analysis
  • With USB2.0 CY7C68013A, BULK transmission type, SLAVE FIFO mode interface. Stable and high speed.
  • USB power supply 5V, current 50mA~250mA. No need external power supply.
  • Software auto upgrade.



Note: Specifications can be changed, added or subtracted without notice in our constant efforts for improvement.